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I assume the state machine uses the same clock that synchronizes the asynchronous inputs, so recovery and removal analysis should have caught any timing problem for these signals if they are asynchronous to the state machine (as opposed to just asynchronous to Clk coming into the FPGA).
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The safe_fabric_transmit_req[1:0] inputs are registered with the same clock as the FSM reading these signals.
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If they're not in the always block sensitivity list for the state machine registers, then they should be covered by setup and hold analysis rather than recovery and removal analysis.
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The registered signals (I believe this makes them synchronous now) are in fact in the sensitivity list (the state machine transition and output logic is in an always @ * block)
I am not clear what purpose the recovery and removal analysis plays in this - I'll read up and maybe it will give me some ideas.
Honored Contributor
