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Altera_Forum
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17 years ago

State machine transitioning into illegal state

I am working with a simple state machine with 4 states. The state machine is properly detected by Altera's state machine optimizer, and the state diagram it produces is correct. When I probe t...
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Altera_Forum
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17 years ago

What is the timing relationship between the FSM clock and async inputs?

Is it possible that one of the async inputs is a pulse shorter than 1 FSM clock period?

If so then it may not be correctly registered by your retime logic

Just a thought.