Forum Discussion
BigSid
Occasional Contributor
Occasional ContributorState Machine Bus Name Format
I'm using Quartus v 13.1 for Cyclone III. The State Machine Wizard only seems to allow input/output bus names with a name[N:0] format but the compiler flags a 275021 error if bus names aren't in a na...
sstrell
Super Contributor
Super ContributorThe state machine code you generated from the State Machine Editor is VHDL. Is your overall design Verilog or VHDL?
BigSidOccasional Contributor
Occasional ContributorI'm doing the design via schematic entry and have selected VHDL file generation at every step when prompted. However, one of the state machine files that was generated (ROM_Select_State_Machine_inst) is listed in my file folder as a "Verilog File Type" even though I was never asked to select the type. Could this be causing an issue? If so, how can this be corrected?
- sstrell
No, that's the instantiation template for Verilog.
So you're creating a schematic design? Can you share that? This may be in your schematic design, not the state machine code.
