State Machine - CASE\WHEN and glitches

By nature of synchronous logic, the state of combinational signals is only evaluated at clock edges. Glitches seen in the these signals at other times are meaningless.

If you intend to generate any glitch-free output signals, they need to be registered however.

At first view, the design implements a regular FSM scheme. The state variable is registered correctly. As wiith every FSM, there might be timing issues brought up by asynchronous input signals that aren't registered before entering the state machine logic.

So simple question, where do you see glitches? Are you sure they actually involve problems for design operation?