[STA] Timing Constraints for synchronizers

No, A multi-cycle path applies for a single path where a register is only active (enabled) for a single clock cycle with other clock cycles in between. Eg, you have a clock enable that is only high every 3 clock cycles, then you know you have a 3 cycle MCP, with 2 clocks of hold. In synchronisers, each register is clocked at full rate, so need to be timed as normal.

You may have MCPs if you have some slower form of hand-shaking that has a known timing relationship, then MCPs may be valid. But if it is a standard 2 reg synchroniser, only false paths are valid (or maybe a relaxed max delay constraint to prevent the registers being placed too far from each other).