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Suhas_P_Intel's avatar
Suhas_P_Intel
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7 years ago

STA report using Quartus 18.0 pro

The clock period and the frequency in the attached spreadsheet for the constraints specified do not match constraints and each other. The desired frequencies are specified by using clock edges of uCl...
Suhas_P_Intel's avatar
Suhas_P_Intel
Icon for New Contributor rankNew Contributor
7 years ago

​Thanks for confirming the reporting bug.

Using edges allows me to scale clocks without having to specify a period for each generated clock. I was hoping that the Quartus tool would do all the calculations. I only change the clock period of the source clock when I'm instantiating the PLL by passing correct parameters:

.c_cnt_hi_div0(hi),

.c_cnt_lo_div0(lo),

.output_clock_frequency0(outClockPeriod),

Is this reporting bug likely to be fixed in the next release?