Hi Nurina,
Thank you very much for your reply!
I firstly correct myself that at the full compilation stage this error occurs, not just at rapid recompilation.
The original file is too big to contain even after compression and so I attach a similar project without compilation.
This project is based on Quartus 15.1 standard edition installed on Linux.
If you compile this project directly using the command below, you are likely to find the error attached above.
aoc -v .aoco (project directory) --board c5soc
I personally also has some finding of the errors and would like to share them here.
The text file that records the whole compilation flow of the project is attached as error_file.txt.
The errors are at line 8008 and 8009.
There are some lines just before the error (line 8005-8007):
Info: kernel clk has period: 404.996
Info: kernel clk has multby: 1 and divby: 454
Info: Using adjusted multby: 404996 and divby: 510112584
Multiplying and dividing numbers in these lines give rise to the overflow and probably this is the reason for the error.
Look at these numbers at the stage just after adjust_plls.tcl being called (Line 7417-7424):
Info: Solved VCO for C 454: 404.059997201 8 1 1362309 4000 20 2 (vco m n k r cp div)
Info: Computed PLL settings: fmax m n k c0 c1 r cp div
Info: Computed PLL values: 0.889999993835 8 1 1362309 454 227 4000 20 2
Info: finfpd 50.0
Info: post-div fvco 404.059997201
Info: true fvco 808.119994402
Info: kernel_fmax 0.889999993835
Info: kernel2x_fmax 1.77999998767
One can see that after pll adjustment, the clock speed is determined to be maximum of 0.89MHz (0.8899999) which is nonsense.
Then look at the VCO period 404.059997201, and the multiplier (n=1) the divider (c0=454), they all occur in the lines before the error.
In order to compensate this 404.996 MHz to be 0.89MHz, the system makes decision: *404996 /510112584.
Since the smallest frequency the PLL can achieve is not even 0.89MHz, these numbers do not make sense at all and thus cause errors in the STA.
Above are my analysis and further investigation fount that the slack at line 7341 compensates the clock frequnecy is -1103.311!!
This is a huge number and that is why the clock frequency is so low!!
However, I am not sure whether my analysis is absolutely correct and also I am not sure why Quartus gives such large slack.
Therefore, I would still kindly ask help if you can help me solve this problem.
Thank you again!
Mingqiang
Occasional Contributor
