Splitting SOPC DDR2 control signals to top and bot- cyclone III

I've had the reverse problem...

I'm working on a Cyclone III Development Board and am trying to figure out how to use the DDR2 high speed controller and use the SDRAM as separate top and bottom banks. I'm working in Quartus II 9.1 sp2 with SOPC builder. The documentation clearly states the SDRAM can be used in separate banks or as a single bank I haven't found anywhere where it talks about how to separate them.

I also am looking for a good starting point "standard design" and found the "standard" files included with the Cyclone III board CD are missing many components.

How do I separate the SDRAM into top and bottom banks in SOPC builder?

Do I need a MM clock bridge or tri-state bridge?

Have any of you found a good starting point for a new design?

Thanks!