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Altera_Forum
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15 years ago

Splitting SOPC DDR2 control signals to top and bot- cyclone III

Hi all, I want to use onboard DDR2 SDRAMs on Cyclone 3 development kit (i want to use 64 bit). I designed all SOPC stuff with DQ width 64 (I changed DQ width in modify parameters option of DDR...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

I had a quick look in the "Cyclone III Development Board Reference Manual" and it looks to me that driving it as a single 72 bit RAM should entirely be possible.

I'm not that fluent in Verilog , but send me a .qar and I will give it a try.