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Altera_Forum
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15 years ago

Splitting SOPC DDR2 control signals to top and bot- cyclone III

Hi all, I want to use onboard DDR2 SDRAMs on Cyclone 3 development kit (i want to use 64 bit). I designed all SOPC stuff with DQ width 64 (I changed DQ width in modify parameters option of DDR...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

I'm using the cyclone III development board.

The problem is that the control signals are split between the top and bottom memory "banks". Combining them causes errors during compilation.

Also, confusion is created by the preset available for a 72 bit memory bus which exists in the DDR2 HPC megafunction wizard. It simply doesn't work.