Splitting SOPC DDR2 control signals to top and bot- cyclone III

josyb,

I've been using Verilog and putting the system together manually. The top and bottom control signals cannot be combined and this seems to be a common problem. The board's reference manual never mentions that all the SDRAM can be used at once:

"The data bus can be configured as two separate buses of 32 bits each, or a single 32-bit and a single 40-bit bus." [p. 2-47]

I take this to mean that using the SDRAM as a single, 72 bit wide bus is not possible.