splitting an output bus on a symbol

That screenshot of the schematic should be doing exactly what you described. So when the most significant bit of q (bit offset 2) is high then the TIMR input of instance 'lights' will also be driven high. If you wanted to feed the two LSBs of q (bit offsets 0 and 1) to some other block you would use the same technique of labeling a signal wire with the alias q[0] or q[1], or q[1..0] if you wanted to feed those into a 2-bit bus connection.

I suspect the wiring is fine and something else is causing the problem. If you are synthesizing this logic and want to see how it's behaving you could wire q[2] out to a pin and look at it with a oscilloscope or signaltap it to see if it's asserted when you expect it to be. I suspect you have a modulo 5 counter driving q[2..0] so I would expect that to behave by driving q[2] high for a single clock cycle, every 5 clock cycles. If that's not what you are suspecting then that is most likely the issue. Also double check what's driving the reset port of that mod5 instance to make sure it's only being reset when you expect it to.