SPI slave clock crossing domain?

I agree, performing all operations using the 200MHz system clock should be fine especially given that the external SCLK is only 20MHz max. This allows you to avoid having to deal with clock crossings and like others have said with such a high system frequency that gives you many internal clocks of wiggle room.

To time everything you could use a modulo counter running on the system domain then you determine which count values cause outputs to transition or inputs to be sampled on. This way if your timing is off you just change the counter thresholds to retime it. The counter can be used to generate the SCLK as well (if you have ever built a PWM it's the same idea). If your SCLK needs to be programmable then you would make these thresholds set with registers that you control with something outside of the core like a processor or whatever is running the show.