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Using separate synchronizers for the SPI input signals is basically O.K. Standard SPI timing has sufficient margin to allow for skew and jitter in the resampled signals.
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Thanks Mr.FvM for this opinion. I got it.
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I would be however worried about the uncomfortable high 200 MHz system clock, which can work for simple digital logic but isn't well suited as general system clock in my view. I have implemented 20 MHz SPI slave units with more compatible 40 MHz system clock, running the SPI unit in the SCK domain with domain crossing data path.
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I also have a little worry about system clock frequency (200 MHz). If I must select a high frequency for system clock so that it is just used for synchronizing SPI signals from SPI clock domain to system clock domain, this selection may not be suitable.
As your information, your implementation has 2 clock domains separately: system clock domain ans SPI clock domain. The SPI logics are processed at SPI clock domain mainly. A domain crossing (synchronization) will be used if there is any data/control signal used between system clock domain and SPI clock domain.
I will consider about your method of implementation in my design.
Thanks.
Honored Contributor
