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If you're implementing and SPI slave in the FPGA, with such a high system clock frequency (200MHz) - then I recommend you treat SCK as a signal, not a clock. Use your system clock to shift SCK through a shift register, allowing you to detect the clock edges. You can then shift data into or out of your system based on the position of these edges and (of course) the state of SS.
The only (slightly) tricky aspect of such a scheme is deciding when to drive SDO when the host is trying to read from your slave peripheral. However, with such a high system clock to SCK frequency ratio you will have ample time to detect the clock edges and prepare the appropriate data for driving back to the master.
Cheers,
Alex
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Thanks Mr.a_x_h_75 for giving your opinion.
I initially select high system clock frequency (200 MHz) for treating SCK as a signal purpose. My intention is to move all SPI slave signals (SS, SCK, SDI) from SPI clock domain to system clock domain, then I will treat the moved SPI signals as signals at system clock domain. At system clock domain, I will detect the edge(s) of SCK, then I will process all SPI processing at system clock domain.
I got your idea about SDO driving at system clock domain so that SPI master can detect data at SDO.
Thanks.
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