SPI slave clock crossing domain?

Using separate synchronizers for the SPI input signals is basically O.K. Standard SPI timing has sufficient margin to allow for skew and jitter in the resampled signals.

I would be however worried about the uncomfortable high 200 MHz system clock, which can work for simple digital logic but isn't well suited as general system clock in my view. I have implemented 20 MHz SPI slave units with more compatible 40 MHz system clock, running the SPI unit in the SCK domain with domain crossing data path.