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Altera_Forum's avatar
Altera_Forum
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7 years ago

SPI slave clock crossing domain?

I have a question about synchronization between clock domains in SPI slave. I need to design a SPI slave module, which has SS (slave select), SCK (SPI clock), SDI (data in from master), SDO (Data ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
7 years ago

If you're implementing and SPI slave in the FPGA, with such a high system clock frequency (200MHz) - then I recommend you treat SCK as a signal, not a clock. Use your system clock to shift SCK through a shift register, allowing you to detect the clock edges. You can then shift data into or out of your system based on the position of these edges and (of course) the state of SS.

The only (slightly) tricky aspect of such a scheme is deciding when to drive SDO when the host is trying to read from your slave peripheral. However, with such a high system clock to SCK frequency ratio you will have ample time to detect the clock edges and prepare the appropriate data for driving back to the master.

Cheers,

Alex