SPI interfacing + Shift Register

always @ (posedge clk)

sr_a <= sr_b;

I don't mean to be sarcastic, but that's it if the SRs are in code, just like any other register transfer. I'm thinking you might be asking something else. Please explain what you've done and what difficulties you're having.

Ok thanks for you reply:

Am trying to implement an SPI for an ADC, i have designed the ASM, written the code partially.

I have a master and a slave, master been my spi interface, slave my ADC, so i want to send a signal to my ADC then transfer the data in the Slave(ADC) into the Master(SPI interface).. the data's are stored in a shift register in both master and slave, data width 12bits.....

The problem i was having was with the transfer from slave shift register to master, but it seems i didn't send the right control/config bits hence was experiencing problems.

Thanks for now...

What you might want to do is make a simple state machine using VHDL or verilog, whatever you are most comfortbale with...

define a 12-bit register that is to store your data say SHIFT_REG(11 downto 0)....

and then make a state machine with 12-states, and in each state it checks the state of the input port, and depending on its value, it sets the value of the corresponding bit in SHIFT_REG. If you are still interested, i can send you some code to explain what is going on better..

cheers,

Kushan.

This is another implementation of an 8-bit shift register shift_register in VHDL...completely different from my previous suggestion.....

library ieee;

use ieee.std_logic_1164.all;

entity SHIFT_REGISTER is

port (DIN : in std_logic; -- system inputs

DOUT : out std_logic_vector(7 downto 0); -- system outputs

ENABLE : in std_logic; -- enable

CLK,RESET : in std_logic); -- clock and reset

end SHIFT_REGISTER;

architecture RTL of SHIFT_REGISTER is

signal TMP: std_logic_vector (7 downto 0);

begin

process(CLK,RESET)

variable i: integer:= 0;

begin

if RESET = '1' then

TMP <= "00000000";

elsif rising_edge(CLK) then

if (i = 8) then

DOUT <= TMP;

i := 0;

else

TMP(i) <= DIN;

i := i + 1;

end if;

end if;

end process;

end RTL;