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tnehowig's avatar
tnehowig
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5 years ago
Solved

SPI (3-Wire Serial) Intel FPGA IP sending 16 bits for every byte write

Hello, I'm having an issue with the SPI port sending out 16 clock cycles every time I try and write a single byte using a NIOS2f. I've verified that the Data Register Width is set to 8 in Platfo...
  • SyafieqS's avatar
    SyafieqS
    5 years ago

    Hi Tyler,

    Glad you had solved the issue. Most of the time, it is always recommended to regenerate you IPs. The feature you said if you turn it on, it will automatically generates IP before compiling the design as it indirectly terminates the manual way where you generate in PD --> add new .qip --> and recompile.

    Thanks,

    Regards

tnehowig's avatar
tnehowig
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5 years ago

I was able to figure out this problem.

It was because Quartus was not regenerating the design files for the IP cores when compiling. So even though my NIOS thought it was writing 8 bits to the SPI IP, the SPI registers were still 16 bits wide.

To fix it, I opened the project in quartus, went to tools > options > IP settings and checked the radio button next to Always regenerate design files for IP cores.