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Altera_Forum
Honored Contributor
14 years agoGreetings
Greetings. Thanks for the responses. I am using VHDL. I tried the vsim -t 1 ns .... and bumped the simulation up to 100ps however modelsim did not like that one bit an threw this error at me # ** Fatal: (SIGFPE) Floating point exception.# Time: 200 ns Iteration: 2 Process: /tb_top/vcs_wrap_inst/vcs_2_dcb_inst/dpa0_inst/altlvds_rx_component/stratixiii_pll/u4/line__10872 File: libs/libs/altera_mf.vhd# Fatal error in Process line__10872 at libs/libs/altera_mf.vhd line 11040# # HDL call sequence:# Stopped at libs/libs/altera_mf.vhd 11040 Process line__10872 perhaps it has something do do with the PLL's in this design. I do not know what a Altera IP netlists is an unfortunatly could not expound upon that one. I am using modelsim 6.5 PE and running it on a windows i7 2.7ghz laptop with 8gigs of RAM. The deisgn, I didn't write. I am in the process of trying to figure out how it works and then modifying the clocks. Hope this helps.... Thanks again for the help Bill