hmm, you should not need to make a new project. changing the device settings and recompiling the design should be all that is necessary. i know that when I change from spd grade 8 to spd grade 7 I get more slack in time quest.
I'd say double and triple check it. Is the failing nodes for the alt tck clk or something like that? Or are you failing timing for part of your own logic? keep in mind if you are passing timing, that quartus is probably not trying to optimize your design further than meeting all of your timing constraints. Meaning it will only do what is good enough to meeting timing for your design for the chosen device and speed grade.