Specifying the latch edge for DDR output timing

For anyone who's interested, it seems that it is now possible to do what I want in Quartus II 7.1. It seems that if the external chip has output/input delays specified for both edges of the clock, then TimeQuest will by default analyze the worst-case launch/latch relationship for both the rising and falling external edges, regardless of which one is the worst-case relationship overall. You can then specify the one that you don't want as a false path.

So, take TD_low_phase_reg in my example above. TimeQuest will now analyze both a setup latch-launch of 4ns (for a falling latch edge, which is a false path in the above design) _and_ a latch-launch of 8ns (for a rising latch edge, which is correct). And for hold timing it will also analyze both a launch-latch of 0ns (which is correct) and a launch-latch of -4ns (which is extraneous).

To cut the unwanted paths, one then just adds the following to their SDC file:

set_false_path -from *|TD_low_phase_reg  -fall_to TXC
set_false_path -from *|TD_high_phase_reg -rise_to TXC

Naturally, for this to be safe, the registers must not fan-out to any other TXC-clocked destinations.

Note that the changes in TimeQuest's behaviour will apply to your DDR receive timing too, but you don't need to do anything special there because the overall worst-case there is also the correct one.

For people doing new DDR designs, I'd recommend this over just adding extra register stages like I did before. After the fit got even more cramped in my part, I had to start playing with the number of register stages to try and find better fits (often failing), but now with the above I don't need any extra register stages at all and it passes timing analysis every time (and real-world testing, too).