Specifying the latch edge for DDR output timing

Wow, that'd be great. Here's a simple VHDL design I whipped-up just now that should demonstrate the problem.

library ieee;
use ieee.std_logic_1164.all;
entity tight_ddr_test is
  port (
    TXC : in std_logic;
    TD : out std_logic_vector(3 downto 0);
    byte : in std_logic_vector(7 downto 0)
  );
end entity;
architecture tight_ddr_test of tight_ddr_test is
  signal TD_high_phase_reg, TD_low_phase_reg : std_logic_vector(3 downto 0);
begin
  process (TXC, TD_high_phase_reg, TD_low_phase_reg)
  begin
    if TXC = '1' then
      TD <= TD_high_phase_reg;
    else
      TD <= TD_low_phase_reg;
    end if;
  end process;
  process (TXC)
  begin
    if rising_edge(TXC) then
      TD_low_phase_reg <= byte(7 downto 4);
    end if;
  end process;
  process (TXC)
  begin
    if falling_edge(TXC) then
      TD_high_phase_reg <= byte(3 downto 0);
    end if;
  end process;
end architecture;

TXC and TD correspond to real ports on my FPGA, whereas "byte" corresponds to the result of previous internal logic. The important part is that the registers are each loaded a half cycle before their result will be enabled in the multiplexer. There's no need for that above, of course, but you'd need it if the timing was tight like it is for me. (Sticking lots of combinational logic in the "<= byte(? downto ?)" lines might simulate that.)

For the SDC file, let's say that TXC has a period of 8ns and the setup and hold times for the destination chip are both 1ns. If we WEREN'T loading the registers in advance, then we could just write this:

create_clock -name TXC -period 8 
set_output_delay -clock TXC -min -1 ]
set_output_delay -clock TXC -max 1 ]
set_output_delay -clock TXC -clock_fall -min -1 ]
set_output_delay -clock TXC -clock_fall -max 1 ]

But since we ARE loading the registers in advance, that doesn't work. TimeQuest assumes, e.g., that we want TD_high_phase_reg to be latched by the destination chip on the rising edge right after we load it.