Contributor
ContributorHi YY.
Thank you.
As about your answer.
About my first question - as for the data path, there are no constant values on DATAINHI and DATAINLO. DATAINHI and DATAINLO connected to synchronizers, which are in turn connected to input ports.
And yes, output of the PLL is connected to the MUXSEL, CLKHI and CLKLO.
So it is a strange situation, where as I understand, we need to consider the whole DDIO and a mux as its ending element as a one trigger-like sequential element, which launches data to the output port.
My question was is it a right explanation, or not. It looks like previous customer (sstrell) who tried to answer that question said "it doesn't make sense that you're seeing data path analysis with a PLL output as the from node."
So it is an interesting case, isnt' it?
As my second question - maybe my question was not descriptive enough, my question was not why I'm seeing 2ns in the latch edge time under Data Required Path,
but why in the Detailed Data Path report we start the clock Path from the input pin and it starts from 2 ns?
Again, I can post my question:
"clock gets shifted inside PLL, and the right report for Data Required Path should start from 0 ns time and should get a 2 ns inside the PLL.
So the second question is - why it is so? There is no reflection of clock phase shift inside detailed path analysis - the shift is incorporated at the start of the analysis."
I can try to explain that - for example - "clock shifts inside PLL aren't represent in the timing path report".
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Best regards,
Ivan
