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IDeyn's avatar
IDeyn
Icon for Contributor rankContributor
7 years ago

Source Synchronous representation in TimeQuest - FPGA is a transmitter

Hi all. I have some things to discuss about Source Synchronous representation in TimeQuest. I attached the project, which is slightly modified version of Source Synchronous Analysis with TimeQuest ...
KhaiChein_Y_Intel's avatar
KhaiChein_Y_Intel
Icon for Regular Contributor rankRegular Contributor
7 years ago

Hi Ivan,

The DATAINHI and DATAINLO have constant value and the output of the PLL is connected to the MUXSEL/CLKHI/CLKLO of the ddio. Besides this, the clock relationship is 2ns, which is why you see 2ns in the latch edge time under Data Required Path.

Thanks.