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IDeyn's avatar
IDeyn
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6 years ago

Source Synchronous representation in TimeQuest - FPGA is a transmitter

Hi all. I have some things to discuss about Source Synchronous representation in TimeQuest. I attached the project, which is slightly modified version of Source Synchronous Analysis with TimeQuest ...
sstrell's avatar
sstrell
Icon for Super Contributor rankSuper Contributor
6 years ago

This is a stupid question, but are the correct clocks from the PLL connected to the data DDIO (and clock DDIO) in your design? Like you said, it doesn't make sense that you're seeing data path analysis with a PLL output as the from node.

#iwork4intel

  • IDeyn's avatar
    IDeyn
    Icon for Contributor rankContributor
    6 years ago

    Hi sstrell.

    Yes, I'm sure, that clocks from the PLL are connected properly to the DDIO. I attached a simple project, and just've checked it.

    Thank you.

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    Best regards,

    Ivan

  • IDeyn's avatar
    IDeyn
    Icon for Contributor rankContributor
    6 years ago

    Hi sstrell.

    Is there any update for an issue, did you see the attached project?

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    Best regards,

    Ivan