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Altera_Forum
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10 years ago

Source Synchronous mode in different quartus version

hi, everyone, I have a design using alt_pll Source Synchronous mode, and I make the data input pin "rx" an PLL Compensation assignment. When builded with Quartus 9.1, the "rx" input register...
Altera_Forum's avatar
Altera_Forum
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10 years ago

What's your FPGA family? With Cyclone III/IV, I see always fast input registers used for serial links. No change in Quartus 13.

Frank