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Honored Contributor
Honored ContributorSource Synchronous Interface Input and Output Delays
Hi Everyone, This is my first post and I tried looking for a solution before asking it here. I am new to static timing and have been studying source synchronous interfaces and how to constrain ...
Altera_ForumHonored Contributor
Honored ContributorFor source synchronous input, a virtual clock drives the "upstream" device (the launch clock) and the clock generated by that device is the base clock into the FPGA (the latch clock or a PLL-generated clock from that incoming base clock).
For source synchronous output, the launch clock is the clock you use to clock out the data, usually from a PLL. For the latch clock, you create a generated clock on an output of the FPGA. This is the only situation for an I/O interface where there is no virtual clock. See this online training for details: https://www.altera.com/support/training/course/ocss1000.html
