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Schroeti's avatar
Schroeti
Icon for Occasional Contributor rankOccasional Contributor
4 years ago

Source synchronous interface clocks: "Asynchronous (Timed Unsafe)"

Hi. I have a FPGA (Cyclone 10 GX, Quartus prime pro 20.4) design which is the sink of 2 independent source synchronous interfaces. The clock edges are center aligned to the data. One of the interfa...
Schroeti's avatar
Schroeti
Icon for Occasional Contributor rankOccasional Contributor
4 years ago

Now I have a interesting problem on this: With a signal tap in the design applied to the avalon mm interface of the problematic module it works.
Programmed with the .sof the module works.
Programmed with the .jic it fails to work.

What could be the side effects of the signal tap in this case?