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Schroeti's avatar
Schroeti
Icon for Occasional Contributor rankOccasional Contributor
4 years ago

Source synchronous interface clocks: "Asynchronous (Timed Unsafe)"

Hi. I have a FPGA (Cyclone 10 GX, Quartus prime pro 20.4) design which is the sink of 2 independent source synchronous interfaces. The clock edges are center aligned to the data. One of the interfa...
Ash_R_Intel's avatar
Ash_R_Intel
Icon for Regular Contributor rankRegular Contributor
4 years ago

Hi,

Sorry for the late response. As you are constraining both the interfaces as per the AN, please check the timing report for the critical path(s). It is possible that the issue may lay somewhere else in the design.


Regards.