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Schroeti
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4 years ago

Source synchronous interface clocks: "Asynchronous (Timed Unsafe)"

Hi. I have a FPGA (Cyclone 10 GX, Quartus prime pro 20.4) design which is the sink of 2 independent source synchronous interfaces. The clock edges are center aligned to the data. One of the interfa...
Schroeti's avatar
Schroeti
Icon for Occasional Contributor rankOccasional Contributor
4 years ago

What I forgot to mention is that the interfaces always work when the over all logic usage of the design is relatively low.