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Altera_Forum
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14 years ago

Source Synchronous Interface - Hold Failure

Hi all, I've a design in which FPGA receive data in DDR with the clock (200MHz) and they are edge aligned. So FPGA shall shift clock 90° in order to capture data correctly and for that I've ins...
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Altera_Forum
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14 years ago

The duty cycle variation is one component of clock jitter and it affects both edges.

I believe you think that only falling edge is affected but that is not right.