Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

Source Synchronous Interface - Hold Failure

Hi all, I've a design in which FPGA receive data in DDR with the clock (200MHz) and they are edge aligned. So FPGA shall shift clock 90° in order to capture data correctly and for that I've ins...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

I'll have a look at this, I'm not sure it address uncertainty on duty cycle..

I'll take a look at it for sure (could make things simpler to understand).

Thank you for the suggestion