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Altera_Forum's avatar
Altera_Forum
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12 years ago

Source synchronous input clock and no output clock constraints

For my Stratix V design, a source synchronous, 4ns period, input clock is used to clock input data. The output data is clocked out of the FPGA back to the source clock without a TX clock. The externa...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

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set_input_delay -clock { rx_phy_pipe_clk_ext } -max 0.8 [get_ports {phy_mac_*}]

set_input_delay -clock { rx_phy_pipe_clk_ext } -max -0.8 [get_ports {phy_mac_*}]

--- Quote End ---

is that -max twice a typo?