Source synchronous input clock and no output clock constraints

Please look at the TimeQuest User , specifically default relationship and multicycles:

http://www.alterawiki.com/wiki/category:design_entry_and_optimization

In quick, your default setup relationship is the tightest latch - launch edge that is greater than 0. So with my example of -250ps shift, on the input side you probably don't need a multicycle because your setup relationship is 3.75ns and your hold is -0.250ps. If you draw out the waveforms, you can usually see it pretty quickly. If you're ever unsure what the setup or hold is, just run report_timing in TimeQuest and it will tell you the setup and hold relationship that it calculates.

If you do -3ns, and add a multicycle on the output, then your setup relationship is 7ns and hold is 3ns. That starts getting tight because your delay has to be greater than 3ns on the fast corner and less than 7ns in the slow corner. Probably do-able, but it gets tight. (My general rule of thumb is that the slow corner is 2x the fast corner delay).

With a -3ns shift, your setup relationship will be 1ns and hold of -3ns, so you probably do want a multicycle there. I don't know the exact delays you're dealing with, so it's hard to say.

Also note that you can have another output of the PLL. So you might have the input and core logic running off your existing clock, and then at the end transfer it to another tap of the PLL that has a phase-shift. That way you can separate your input timing from your output timing.