Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

Source synchronous input clock and no output clock constraints

For my Stratix V design, a source synchronous, 4ns period, input clock is used to clock input data. The output data is clocked out of the FPGA back to the source clock without a TX clock. The externa...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

If you do a negative phase-shift you probably need a multicycle. For example, if your PLL generated clock is 4ns just like rx_phy_pipe_clk_ext, then the setup relationship is 4ns and hold is 0ns. If you phase-shift the source clock by -250ps, then your default setup relationship is 250ps and your hold is -3.75ns. You probably want a multicycle saying you are targeting the next latch clock:

set_multicycle_path -setup -from [get_clocks <pll_clk_name>] -to [get_clocks rx_phy_pipe_clk_ext] 2

In the case above, that would made the setup relationship 4.25ns and the hold relationship 0.25ns.