Source-synchronous constraints with the -reference_pin option

Hi Jason,

The only reason for using a PLL is to have control over the phase relationship between the outgoing clock (the clock that the external device sees) and the internal FPGA clock that clocks out / latces data to / from the external device. If this is an SDRAM device you are interfaceing then typically you would use a PLL to compensate for the FPGA and SDRAM delays. You want to make sure that the SDRAM latches the data when it is stable and you want to make sure the FPGA latches data from the SDRAM when it is stable.

As for thew -reference_pin option, I have never used it. What I would do is to create a generated clock for the output clock. Something like:

create_generated_clock -name clk_mem -source CLK_100MHZ [get_ports SRAM0_CLK]

and then to use set_output_delay using this clock as the reference.

set_output_delay -clock { clk_mem } 1.0 [get_ports {S0DATA

[*]}]

(typing this from memory, so syntax may not be 100% correct).

Regards,

Niki