Forum Discussion
Altera_Forum
Honored Contributor
14 years agoNo I think only std_logic and std_logic_vector are supported.
As Quartus / SOPC builder supports both VHDL and Verilog there are lots of restrictions on the signal types you can use. You will probably need to put everything in a big std_logic_vector (or distribute on several signals) and remap to a record or array in your code.