Forum Discussion
Altera_Forum
Honored Contributor
18 years agoThank you very much Klaus, SOPC now finds the components but I get all kinds of extra errors I'm afraid. Any ideas why each of my components now produce the following error :
Error: TestComponent_0: Error (10670): Verilog HDL or VHDL error: cannot create XML design interface for design file TestComponent.vhd. File: C:/SCM/Branch-Quartus-v7-1/lib/sopc/TestComponent/hdl/TestComponent.vhd Line: 1 Error: TestComponent_0: Quartus II Analysis & Synthesis was unsuccessful. 1 error, 0 warnings Error: TestComponent_0: Processing ended: Mon Oct 22 16:26:15 2007 Error: TestComponent_0: Elapsed time: 00:00:04 Error: TestComponent_0: Failed to analyze port width. If I copy the components to the \ip subdir of my project I don't get this error. The library.ipx file is located in C:/SCM/Branch-Quartus-v7-1/lib/sopc