SOPC component with unespected cicle

Hi.

I have create a component with sopc (a simple sram) and it work fine.

I'm working with Quartus 8.1.

Checking with signal tap I have discover a strange behaviour.

Any read, and only read, cicle byte or word are followed by a read dummy

cicle with all byte enable deasserted.

Any idea about?

Thanks.

Paolo

trace dump image

http://img16.imageshack.us/my.php?image=oedummyrh3.jpg