[SOPC Builder] pixel treatment in different clock domain

No I mean one DCFIFO. The dual clock FIFO has two clocks, one on each side. You connect one side to the data source, with its clock, and the other side to the data destination, with its clock.

Are you connecting your modules though SOPC Builder or QSYS? If yes, you will find a stream dual clock FIFO component that you can directly use to make the connection, in the memories category if I remember correctly.