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Altera_Forum
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17 years ago

SOPC builder - std_logic ports/signals must be width 1

I've got an SOPC builder custom component that I just added (called "ddr2_ctrl2" below). I'm getting an odd error when trying to generate the system: Error: ddr2_ctrl2: Internal error: std_logi...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

Hello,

I have the same problem but I haven't found a solution yet. I import my project from Quartus 7.2sp2 into Quartus 8.1 and then starts the SOPC generation. I don't have any problem with Quartus 7.2 but I get the error "std_logic ports/signals must be width 1" with Quartus 8.1. What did you do to solve the problem?

Thanks in advance for your help.