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Altera_Forum's avatar
Altera_Forum
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17 years ago

SOPC builder - std_logic ports/signals must be width 1

I've got an SOPC builder custom component that I just added (called "ddr2_ctrl2" below). I'm getting an odd error when trying to generate the system: Error: ddr2_ctrl2: Internal error: std_logi...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

Apparently there were extra files in the component file list that were not actually used for the component. Removing these fixed the problem.