SOPC Address Funny

Hi,

I have tracked the problem down to the de-interlacer core I have in the design. I have two separate Avalon MM buses in my design - the one is the control bus (8 bit address, 16-bit data, with two masters) and the other is a memory bus connecting the a frame buffer and the de-interlacer to an SDRAM controller (24-bit address, 16-bit data)

What I have seen is if I change the Avalon MM MAster Port Width setting in the DeInterlacer parameters to 64 bits or more, then I start seeing errors regarding memory range overlaps and invalid locations on my control bus side. I cannot see why the address width on the one bus should affect the address width on the other bus. I have no bridges between the two buses. They are completely separate. The deinterlacer is not connected to the control bus at all.

BadOmen, it seems that what you are saying is happening, but I cannot see why a wide master on one bus affects the other bus.

Regards,

Niki