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Altera_Forum's avatar
Altera_Forum
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18 years ago

slow slew rate on CII

I am using Q7.2 and one of the FireflyII boards (CycloneII), and I want to generate a fast edged clock signal. Even after setting current strength to max in the pin assignments, the slew rate is too ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
18 years ago

Slew rate, as in rise time, as in V/us or V/ns.

My signal is ~3v/20ns and nowhere near the 1ns or so I would expect with 3.3v IO. CII parts are supposed to do 200-400Mhz+ TTL IO rates. My signal does pass thru a connector, but there is no way it has the kind of parasitics which would cause this. All I could think of is a global setting of some kind, or that when I changed my current strength setting it was ignored. The only ones I am aware of are:

IO Standard,

Current strength,

Slow slew rate,

Digital termination (OCT),

Various power settings?

The only settings files I am aware of are *defaults.qdf, *.qsf

If someone has the full picture of what the relevant settings are, please let me know.