Slack:Not operational: Clock Skew>Data Delay ...

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Hi All,

In Quartus II,

the classic timing analysis report shows:

Slack:Not operational: Clock Skew>Data Delay,

but,when i download the whole design to the fpga,

it can works without any error.

meanwhile, when i right-click the red information in the report

and chose "locate in RTL viewer" , could see the two register

use two different clock, which is right a part of the design.

i don't think this situation should be analyzed with the regulation

of "clock hold analysis" ,for the two register use different clock.

but how should i deal with the error information (with red color)

in the classic timing analysis report?

Thank you!

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Hi,

that means you have a clock domain crossing here. Connecting the register simply together will not work in all cases. There is a lot of stuff in the forum regarding clock domain crossing.

Kind regards

GPK

Gerd

Pletz,thank you for your reply.

the rtl view image shows in this link web:

http://hi.baidu.com/cowoho/album/item/96120d3304ed38d91b4cff5a.html

it seems not a example that should be analyzed with the regulation of "clock skew< or > data delay", but in the Quartus II software,it was judged to "clock > data delay",in the classic timing analysis report table with red color.when right-click the red information in the report and chose "locate in RTL viewer" ,we could see the image like above.

i want to ask:is this design showed in the image reasonable&#65311;i think if "clk1/clk2" could fit "data1/data2" in timing, there should not be errors in this part, really? and, if yes,could i neglect the warn of quartus?

waiting for help...thanks!