Slack issue in dual clock FIFO

An asynchronous reset(even if it's synchronized) should generally only be used to reset an entire domain(and usually an entire device or something on that scale) and not as logic. Static timing analysis does not time the logic being asynchronously reset to downstream logic that is not being reset, so you're always susceptible to this unless reseting everything. (If it did time it, closing timing would be significantly more difficult. For example, if you had 10ns period and a data path from reg A to reg B that was 8ns long, so it met timing, but now asynchronously reset A but not B and expected that to work synchronously and not glitch, then reset -> A -> B would all have to be less than 10ns, so now two paths would have to be under your clock period instead of just one.)