Slack issue in dual clock FIFO

One thing to note on this subject, especially around dual-clock fifos and resets is that FIFO reset clears the flags and usedwds asynchronously as I understand it. This means that if you have logic, say a state machine in the read domain looking at rdusedwds that is not reset with the FIFO you need to re-register the rdusedwds (or provide some other method of handling this case) in the read domain to keep from glitching it since rdusedwds may be cleared asynchronously. Last I checked, the sync circuit Altera adds to the FIFOs does not cover this condition. I see this situation a lot with high-speed link bring-up or hot-plugging.