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Note that Altera originally just added an option to synchronize the write side, since that was deemed all that was necessary for the reasons stated above. But most users didn't understand why the read didn't need to have its reset synchronized too and kept asking why we didn't do it. Rather than constantly explain it, it's easier to just add the ~2 registers for read side synchronization.
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The case of OP is having wr_reset separate from rd_reset. In this case both resets need to comply with timing at deassertion (recovery/removal). Imagine the case when the write clock is 4 times faster than read clock; the fifo may not be empty by the time rd_reset is deasserted and will soon increment.
If reset is only synchronised to write clock and then applied to both sides then yes and provided the user does not read immediately there is no need to worry about recovery/removal at rd side but then it is up to the tool to automatically set false path in such hidden corner.
In fact I see the new fifo desin of separate wr/rd reset as a potential pitfall unless the user is aware of internal delay of rd reset and take that into account when activating the rd logic.
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