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Altera_Forum
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11 years ago

Slack issue in dual clock FIFO

Hi. I have dual clk fifo in my project for Stratix V. Write clk - 250 MHz, read clk - 100 MHz. Fifo has aclr signal that is equal to wr_rst OR rd_rst. wr_rst is synchronous to 250 MHz, rd_rst is s...
Altera_Forum's avatar
Altera_Forum
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11 years ago

Note that Altera originally just added an option to synchronize the write side, since that was deemed all that was necessary for the reasons stated above. But most users didn't understand why the read didn't need to have its reset synchronized too and kept asking why we didn't do it. Rather than constantly explain it, it's easier to just add the ~2 registers for read side synchronization.